A liquid crystal display (LCD) panel is widely used as a computer monitor, a flat TV, a test instrument display and the like. A brief description is made regarding an LCD panel which is a device to be tested by the LCD panel test system of the present invention. An LCD panel includes a large number of pixels (picture elements) aligned in a matrix manner.
FIG. 3 shows an example of structure in an LCD panel made of amorphous TFT. In the LCD panel 10, a large number of gate lines 19.sub.1 -19.sub.m which are parallel with one another are provided on a quartz substrate. A large number of data lines 20.sub.1 -20.sub.n which are parallel with one another and perpendicular to the gate lines are also provided on the substrate. At each cross point of the gate line 19 and the data line 20, a pixel TFT (thin film transistor) 14 is established.
In each pixel TFT 14.sub.ij (14.sub.11 -14.sub.nm), a gate is connected to the gate line 19, a source is connected to the data line 20, and a drain is connected to an auxiliary capacitor 15.sub.ij (15.sub.11 -15.sub.nm) as shown in FIG. 3. The other end of the auxiliary capacitor 15.sub.ij is commonly connected to a ground terminal 22. In this manner, a large number of pixels each of which is formed of the pixel TFT 14.sub.ij and the auxiliary capacitor 15.sub.ij are aligned in a matrix manner on the substrate.
The number of pixels in the LCD panel is, for example, 307,200 (640.times.480) in the VGA (Video Graphics Array) standard, 480,000 (800.times.600) in the SVGA (Super Video Graphics Array) standard, and 786,432 (1,024.times.768) in the XGA (Extended Graphics Array) standard. In an EWS (Engineering Work Station) application, the number of pixels is further required to be as large as 1,310,720 (1,280.times.1,024).
The gate lines 19.sub.1 -19.sub.m are connected to corresponding registers in a row select shift register 11 having m stages of registers. The data lines 20.sub.1 -20.sub.m are connected to corresponding video lines 21 through column select switches 13.sub.i (13.sub.1 -13.sub.n). The column select switches 13.sub.i are made of thin film transistors. Each gate of the thin film transistor of the column select switch 13 is connected to a corresponding register in a column select shift register 12 having n stages of registers.
When the number of pixels is large, for achieving a high speed operation, a plurality of video lines 21 and column select shift registers 12 may be employed in the LCD panel. In such a case, the number of video lines is typically 2-6, but sometimes, the video lines up to 24 may be used. The number of column select registers 12 may be 2-4 which are perpendicular with one another.
The row select shift register 11 has a terminal DY for receiving a vertical drive signal and a clock terminal CLY for receiving a vertical operation clock. In receiving the vertical drive signal and the vertical operation clock, the row select shift register 11 sequentially generates a high level signal at one of the registers for every horizontal sweep. Namely, the high level signal is provided sequentially at one of the gate lines 19.sub.1 -19.sub.m for every horizontal sweep.
The column select register 12 has a terminal DX for receiving a horizontal drive signal and a clock terminal CLY for receiving a horizontal operation clock. In receiving the horizontal drive signal and the horizontal operation clock, the column select shift register 12 sequentially generates a high level signal at one of the registers for every pixel cycle. Namely, the high level signal is provided sequentially at one of the data lines 20.sub.1 -20.sub.m for every cycle of the horizontal operation clock.
Therefore, for example, during the period when the gate line 19.sub.1 is in the high level, the gate of the column select switch 13.sub.1 becomes high level. As a consequence, the pixel TFT 14.sub.11 goes ON so that the video signal from the video line 21 is charged in the auxiliary capacitor 15.sub.1 through the drain and source of the pixel TFT 14.sub.11. The charge stored in the auxiliary capacitor 15.sub.11 represents the signal level of the incoming video signal.
During the time when the gate line 19.sub.1 is in the high level, the column select switches 13.sub.1 -13.sub.m are consecutively driven to a high level, one by one, by the horizontal operation clock. Thus, the pixel TFTs 14.sub.11 -14.sub.1n are sequentially set to ON so that the video signal from the video line 21 corresponding to the pixel point is charged in the corresponding auxiliary capacitors 15.sub.11 -15.sub.1n. In this manner, all the pixels connected to the gate line 19.sub.1 are swept by the horizontal operation clock. In the next horizontal sweep, the gate line 19.sub.2 is set to the high level, and the horizontal sweep is performed for the pixels connected to the gate line 19.sub.2.
This horizontal sweep is repeated for all the pixels in the LCD panel provided with video signals from the video line 21. When all the gate lines 19 are scanned in this manner, a picture is formed on the LCD panel. Similar to the known television technology, such pictures are produced on the LCD panel several ten times or more per second to show images without flickers.
An LCD panel test system is used for testing LCD panels having a large number of pixels as in the above noted example. Two types of failure are usually exhibited in such an LCD panel, one is line defect and the other is pixel defect. The line defect means an existence of an open circuit in the various lines and components in the LCD panel. Thus, the line defect can be relatively easily identified when testing an LCD panel in performing a conduct/non-conduct test by an LCD test system.
The pixel defect means failures in the pixel, i.e., the charge and discharge operation in the auxiliary capacitors of the pixels. The pixel defect includes open defect in which the auxiliary capacitor is open circuited and short defect in which the auxiliary capacitor is short circuited. When the auxiliary capacitor works properly, the video signal is correctly charged in the capacitor. When the auxiliary capacitor has either the open defect or the short defect, it cannot properly charge the video signal.
Several methods of testing the pixel defect have been introduced. One of the methods is disclosed in the Japanese Patent Publication No. 5-158056 filed by the same assignee of the present invention. This example is described with reference to FIG. 5. In this conventional method, when detecting the pixel defect, a rectangular signal is provided to a common ground terminal 22 of the LCD panel. As shown in FIG. 3, the common ground terminal 22 is commonly connected to all the auxiliary capacitors 15.sub.ij of the pixels. At the same time, voltage levels corresponding to the pixels at the video output lines 21 of the LCD panel 10 are monitored. On the basis of the voltage levels, the pixel defect is detected to evaluate the quality of the LCD panel 10.
The LCD panel test system of FIG. 5 includes a sweep timing generator 30, a test signal generator 31, a high speed switch 32, an impedance converter 33, a sample and hold circuit 34, an amplifier 35, an A/D converter 36 and an image processor 37. The LCD panel 10 in FIG. 5 is shown in more detail in FIG. 3 as discussed above.
In testing the LCD panel 10, a vertical drive signal and a vertical operation clock, both from the sweep timing generator 30, are applied to the DX terminal and the CLY terminal, respectively. Further, a horizontal drive signal and a horizontal operation clock, both from the sweep timing generator 30, are applied to the DX terminal and the CLX terminal, respectively.
As noted above, the common ground terminal 22 is commonly connected to all the auxiliary capacitors 15.sub.ij of the pixels. The test signal generator 31 provides a test signal, such as a rectangular signal, to the common ground terminal 22 of the LCD panel 10. The application timing of the rectangular signal is, for example, at the intermediate of each switching (selection ) period of the pixels. At the timings of the beginning and ending of each switching period, a discharge operation is performed as will be explained later.
When the selected pixel functions properly, an-output signal having a voltage proportional to the test signal is produced at the video terminal 23 through the video line 21 of the LCD panel 10. For example, if the auxiliary capacitor 15.sub.ij in question is short circuited, an output signal having a high level voltage is produced at the video terminal 23. In contrast, if the auxiliary capacitor 15.sub.ij is open circuited, an output signal having a low level voltage is produced at the video terminal 23.
The high speed switch 32 is provided between the video terminal 23 and the common ground. At the beginning and ending of the selection period of the pixels, the high speed switch 32 is driven to ON so as to drain the electric charge stored in the stray capacitances connected to the video terminal 23.
The impedance converter 33 converts high impedance of the output signal at the video terminal 23 to low impedance to be supplied to the sample and hold circuit 34. The output signal from the terminal 23 is sampled at the timing close to the end of the rectangular test signal and holds its voltage for the analysis in the later stages of the test system. The sampled voltage from the sample and hold circuit 34 is amplified by the amplifier 35 whose output is connected to the A/D converter.
Thus, the output signal at the video terminal 23 is converted to a digital signal by the A/D converter 36. The digital signal is provided to the image processor 37 where the voltage levels relative to other pixels are evaluated to determine whether there is any defective pixels in the LCD panel 10.
In this conventional example of testing the LCD panel, the short defect (the auxiliary capacitor is short circuited) of the pixel is easily identified since the output signal from the video terminal becomes substantially large. However, the open defect (the auxiliary capacitor is open circuited) is not easily discernible because of a poor S/N (signal to noise) ratio in the output signals from the video terminal 23.
This is because the stray capacitances on the data lines 20.sub.i and the video lines 21 in the LCD panel 10 are significantly large relative to the selected auxiliary capacitor 15.sub.ij of the pixel. Thus, the output voltage at the video terminal 23 is affected by the stray capacitances whose reactance values are several ten times larger than the auxiliary capacitor 15.sub.ij in question.
FIG. 4 shows an equivalent circuit of one of the pixels in the LCD panel of FIG. 3 when the pixel transistor TFT 14 is ON. In FIG. 4, R8 designates an ON resistance of the column select switch 13.sub.i and R9 designates an ON resistance of the pixel transistor TFT 14.sub.ij. The ON resistance R8 is typically 10K ohm while the ON resistance R9 is typically 1M ohm. Also in FIG. 4, numeral 16 designates a stray capacitance on the data line 20 and numeral 17 designates a stray capacitance on the video line 21. Although the capacitance values of the stray capacitances 16 and 17 are dependent on the size of the LCD panel substrate, typically, the stray capacitance 16 is 5 pF and the stray capacitance 17 is 10 pF. On the other hand, the auxiliary capacitance 15.sub.ij has a capacitance value of about 0.1 pF.
Since the auxiliary capacitance 15.sub.ij of the pixel is less than 1/100 of the sum of the stray capacitances of the data line 20 and video line 21, the voltage change in the capacitor 15.sub.ij between the normal situation and the defective situation in the pixel is very small because of the large stray capacitors. Thus, in the conventional technology, it is difficult to accurately detect the open defect in the pixels of the LCD panel.
Further, in the conventional technology where the rectangular test signal is provided at the common ground terminal and the resultant signal is detected at the video terminal 23, a fine timing adjustment is necessary to discharge the voltages in the stray capacitors by the external switch as described above. Since this test procedure involves the delicate timing adjustment, it is complicated and time consuming.